LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
ENTITY maxii_lamp1 IS
PORT(
clk : IN STD_LOGIC;
leddrv : OUT STD_LOGIC
);
END maxii_lamp1;
ARCHITECTURE maxii_lamp1 OF maxii_lamp1 IS
SIGNAL reg : STD_LOGIC :='0';
BEGIN
leddrv <= reg;
PROCESS(clk)
VARIABLE cnt : INTEGER RANGE 0 TO 50000000 :=0;
BEGIN
IF clk'EVENT AND clk='1' THEN
cnt := cnt+1;
IF cnt=50000000 THEN
cnt := 0;
reg <= NOT reg;
END IF;
END IF;
END PROCESS;
END maxii_lamp1;
|
